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T2801
DECT Single-Chip Transceiver
Description
The T2801 is an RF IC for low-power DECT applications. The HP-VFQFP-N48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closedloop modulation concept. No mechanical tuning is necessary in production.
Features
D Supply-voltage range 3 V to 4.6 V (unregulated) D Auxiliary-voltage regulator on-chip D Low current consumption D Few low cost external components D No mechanical tuning required D Non-blindslot and blindslot operation D Unlimited multislot operation with advanced closedloop modulation (13.824 MHz/ 27.648 MHz and 10.368 MHz/ 20.736 MHz) D TX preamplifier with 0 dBm output power at 1.9 GHz and ramp-signal generator for SiGe power amplifier
Block Diagram
MIXER IF_IN OUT IR MIXER RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN D/A RSSI VCO TX / RX SWITCH LATCH PC TX_OUT TX DRIVER VCO REG AUX REG CP f :n RC CTRL LOGIC f :n PD MCC 3-WIRE BUS GF TX_DATA DATA_HOLD CLOCK DATA ENABLE RX_ON TX_ON PU_RX/TX PU_PLL RSSI IF_TANK IF AMP 1 IF AMP 2 BB_OUT DEMOD_ TANK CF
PU_VCO
VREG_VCO VS_VCO VREG VS_REG VTUNE GND_VCO PU_REG REG_CTRL
CP
LD
REF_CLK
Figure 1. Block diagram
Ordering Information
Extended Type Number T2801-PLT T2801-PLQ Package HP-VFQFP-N48 HP-VFQFP-N48 Remarks Tray Taped and reeled
Rev. A1, 04-Jul-00
1 (24)
Preliminary Information
T2801
Pin Description
MIXER_OUT2 MIXER_OUT1 DATA_HOLD
48 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP 1 2 3 4 5 6 7 8 9 10 11 12 13
47
46
45
44
43
42
41
40
39
38
37 36 35 34 33 32 RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI
RAMP_SET
VS_MIXER
PU_RX/TX
TX_DATA
GND_PLL
PU_PULL
PU_VCO
RX_ON
TX_ON
T2801
31 30 29 28 27 26 25
14
15
16
17
18
19
20
21
22
23
24
VREG_VCO
DAC_DEC
VS_VCO
GND_VCO
REG_DEC
DEMOD_TANK1
Figure 2. Pinning
Pin 1
Symbol CLOCK
Function 3-wire-bus: Clock input
DEMOD_TANK2
BB_OUT
VTUNE
BB_CF
GND1
CP
Configuration
2
DATA
3-wire-bus: Data input
3
ENABLE
3-wire-bus: Enable input
2 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Pin Description (continued)
Pin 4 Symbol REF_CLK Function Reference-frequency input Configuration
5
LD
Lock-detect output
6
PU_REG
Aux. voltage regulator power-up input
7
VS_PLL
PLL supply voltage
Rev. A1, 04-Jul-00
3 (24)
Preliminary Information
T2801
Pin Description (continued)
Pin 8 Symbol VREG Function Aux. voltage-regulator output Configuration
9
REG_CTRL
Aux. voltage-regulator control output
10
VS_REG
Aux. voltage-regulator supply voltage
11
GND_CP
Charge-pump ground
12
VS_CP
Charge-pump supply voltage
13
CP
Charge-pump output
14
VS_VCO
VCO voltage-regulator supply voltage
15
VREG_VCO
VCO voltage-regulator control output
16
GND_VCO
VCO ground
17
VTUNE
VCO tuning voltage input
4 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Pin Description (continued)
Pin 18 Symbol GND1 Function Ground Configuration
19
DEMOD_TANK1 Demodulator tank circuit
20
DEMOD_TANK2 Demodulator tank circuit
21
DAC_DEC
Decoupling PIN for VCO_DAC
VS
DAC_DEC 4.7k VS 10k REG_DEC 21 22
22
REG_DEC
Decoupling PIN for REG
Rev. A1, 04-Jul-00
5 (24)
Preliminary Information
T2801
Pin Description (continued)
Pin 23 Symbol BB_CF Function Baseband filter corner-frequency control input Configuration
24
BB_OUT
Baseband filter output
25
RSSI
Received signal-strength indicator output
26
IF_TANK1
IF tank circuit
27
IF_TANK2
IF tank circuit
6 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Pin Description (continued)
Pin 28 Symbol GND2 Function Ground Configuration
29
RF_IN1
Differential RF input of image reject mixer
30
RF_IN2
Differential RF input of image reject mixer
31
GND3
Ground
Rev. A1, 04-Jul-00
7 (24)
Preliminary Information
T2801
Pin Description (continued)
Pin 32 Symbol TX_OUT Function TX driver amplifier output for PA Configuration
33
VS_IF
IF amplifier supply voltage
34
IF_IN1
Differential IF input of IF amplifier
35
IF_IN2
Differential IF input of IF amplifier
8 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Pin Description (continued)
Pin 36 Symbol RAMP_OUT Function Ramp-generator output for PA power ramping Configuration
37
RAMP_SET
Slew-rate setting of ramping signal
38
RX_ON
RX control input
39
TX_ON
TX control input
40
MIXER_OUT1
270W
41
MIXER_OUT2
Differential mixer output for SAW filter
Rev. A1, 04-Jul-00
270W
Differential mixer output for SAW filter
9 (24)
Preliminary Information
T2801
Pin Description (continued)
Pin 42 Symbol VS_MIXER Function Mixer supply voltage Configuration
43
GND_PLL
PLL ground
44
PU_VCO
VCO power-up input
45
PU_RX/TX
RX/TX power-up input
46
PU_PLL
PLL power-up input
10 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Pin Description (continued)
Pin 47 Symbol TX_DATA Function TX data input of Gaussian filter and modulation-compensation circuit Configuration
48
DATA_HOLD
Data-hold input to keep the latch information in power-down mode
Functional Description
Receiver
The RF-input signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110 MHz or 111 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 (55 MHz/ 55.5 MHz) and finally to an integrated baseband filter BB. For demodulator tuning in production an integrated 5-bit digital-to-analog (D/A) converter is used to control the on-chip varicap diode. is also integrated. The slope of the ramp signal is controlled by a capacitor at RAMP_SET.
Synthesizer
The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). An 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequencydivided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC.
Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing ramp signals at RAMP_OUT for an external power amplifier,
Power Supply
For minimum interference and maximum signal isolation an integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided.
Rev. A1, 04-Jul-00
11 (24)
Preliminary Information
T2801
PLL Principle
RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO fPD CP VCO PA driver Divider Mixer
Phase frequency detector PD
DAC fPD = 3.456 MHz GF_DATA Gaussian filter GF
Controlled phase shifting
Modulation compensation MCC
Reference counter RC REF_CLK 10.368MHz 13.824MHz 20.736MHz 27.648MHz SRC 3 4 6 8
6.912 MHz
1.152 Mbit/s
PLL reference Frequency REF_CLK Baseband controller
TX_DATA
Figure 3.
12 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for an optional DECT band extension. Intermediate frequencies of 110.592 and 112.32 MHz are supported.
Table 1. LO frequencies
Mode TX
fIF/MHz
RX
110.952
RX
112.320
Channel C9 C8 ... C1 C0 C10 C11 ... C29 C30 C9 C8 ... C1 C0 C10 C11 ... C29 C30 C9 C8 ... C1 C0 C10 C11 ... C29 C30
fANT/MHz 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632
fVCO/MHz 3763.584 3767.040 ... 3791.232 3794.688 3798.144 3801.600 ... 3863.808 3867.264 3542.400 3545.856 ... 3570.048 3573.504 3576.960 3580.416 ... 3642.624 3646.080 3538.944 3542.400 ... 3566.592 3570.048 3573,504 3576.960 ... 3639.168 3642.624
fVCO/2/MHz 1881.792 1883.520 ... 1895.616 1897.344 1899.072 1900.800 ... 1931.904 1933.632 1771.200 1772.928 ... 1785.024 1786.752 1788.480 1790.208 ... 1821.312 1823.040 1769.472 1771.200 ... 1783.296 1785.024 1786.752 1788.480 ... 1819.584 1821.312
SMC 34 34 ... 34 34 34 34 ... 34 34 32 32 ... 32 32 32 32 ... 32 32 32 32 ... 32 32 32 32 ... 32 32
SSC 1 2 ... 9 10 11 12 ... 30 31 1 2 ... 9 10 11 12 ... 30 31 1 2 ... 9 10 11 12 ... 30 31
Table 2. Limits
Mode TX RX TX RX Formula
fIF/MHz fmin 110.592 112.320 fmax 110.592 112.320
fANT/MHz 1769.472 1880.064 1826.496 1988.928 2099.520 2101.248
fVCO/MHz 3538.944 3538.944 3538.944 3977.856 3977.856 3977.856
fVCO/2/MHz 1769.472 1769.472 1769.472 1988.928 1988.928 1988.928
SMC 32 32 32 35 35 35
SSC 0 0 0 31 31 31
fANT Ci - fANT Ci-1 = 1.728 MHz for TX: fVCO = 2 x fANT for RX: fVCO = 2 x (fANT - fIF)
Rev. A1, 04-Jul-00
13 (24)
Preliminary Information
T2801
Control Signals
LD PU_REG PU_VCO PU_RX/TX PU_PLL
Table 3.
output, which is active after PLL is locked and test-mode output (according to programmed test mode) hardware power up --> standby of regulator hardware power up --> standby of voltage controlled oscillator hardware power up --> standby of RX/ TX part hardware power up --> standby of synthesizer Logic Standby Standby Hold Register 1 0 X X X X X OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF <0.1 TX Mode RX Mode RSSI Only
DATA_HOLD PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON BB filter Demodulator IF amplifiers and RSSI IR mixer RX switch TX switch TX driver Ramp generator Programmable counter Voltage-controlled oscillator Gaussian filter Phase detector / charge pump Modulation compensation circuit Reference counter Current consumption / mA @ VS = 3.2 V
0 0 X X X X X OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF <0.01
X 1 1 1 1 0 1 OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON ON 54
X 1 1 1 1 1 0 ON ON ON ON ON OFF OFF OFF ON ON OFF ON OFF ON 85
X 1 1 1 1 1 1 OFF OFF ON ON ON OFF OFF OFF ON ON OFF ON OFF ON 80
Serial Programming Bus
Reference and programmable counters can be programmed by the 3-wire bus (CLOCK, DATA and ENABLE). Besides this information additional control bits as phase detector polarity and scaling of charge-pump currents as well as internal currents for Gaussian lowpass filter and modulation compensation circuit can be transferred. After setting enable signal to low condition, on the rising edge of the clock signal, the data status is transferred bit by bit into the shift register, starting with the MSB-bit. After enable returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses have arrived during enable-low condition. The bus then returns to a low current standby mode until the ENABLE signal changes to low again. To keep the information in the registers of the PLL during standby DATA_HOLD must be set to high condition.
14 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Bus Protocol Formats
MSB Data bits D22 1 D21 0 D20 0 D19 1 D18 SC 1 1 1 0 D17 D16 D15 D14 0 D13 1 D12 PS 1 1 D11 D10 GF 0 D9 MCC 0 1 D8 D7 GFCS 0 0 1 D6 D5 D4 0 D3 0 D2 1 D1 CPCS 0 0 D0 LSB Address bit A0 1 1 VCODAC
RC
MC
Standard bit setting:
Word 1 E10 Word 2 0 E9 0 E8 0 E7 0 E6 0 E5 0 E4 MCCS 0 0 0 E3 E2 E1 TEST 0 0 E0 A0 0 0 DEMODDAC
PLL Settings
D22 0 0 1 1 RC (Reference Divider) D21 0 1 0 1 SRC 3 4 6 8
Phase Settings
Phase of GF-Output (Internal Connection) D13 GF-DATA 0 Source 1 Sink
D15 0 0 1 1
MC (Main Divider) D14 0 1 0 1
Phase of MCC-Output (Internal Connection) D12 MCC-Data 0 Inverted 1 Normal
SMS 32 33 34 35
D11 0 1
Phase of CP (Charge Pump) f R > fP f R < fP f R = fP ISink ISource High imp. ISource ISink High imp.
D20 0 0 0 ... 1 1 1
D19 0 0 0 1 1 1
SC (Swallow Counter) D18 D17 D16 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1
SSC 0 1 2 ... 29 30 31
Current Savings Power up/down Settings
D10 0 1 GF (Gaussian Filter) OFF ON
D9 0 1
MCC (Modulation Compensation Circuit) OFF ON
Rev. A1, 04-Jul-00
15 (24)
Preliminary Information
T2801
Current Gain Settings
GFCS (Gaussian Filtered Current Settings) D8 D7 D6 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130%
Pretune DAC Voltage Settings
Pretune DAC Voltage (Internal Connection) D5 D4 D3 fVCO/% 0 0 0 -5 0 0 1 ... 0 1 0 ... 0 1 1 ... 1 0 0 ... 1 0 1 ... 1 1 0 ... 1 1 1 5
Test Mode Settings
CPCS (Charge-Pump Current Settings) (Internal Connection) D2 D1 D0 CPCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% D11 X 0 1 X X 0 1 X E2 0 0 0 0 1 1 1 1 Test Output Pin (Lock Detect) E1 E0 Signal at lock detect output 0 0 Lock detect 0 1 RC out 1 0 PC out 1 1 RC out divided by 2048 (MCCTEST) 0 0 CP tristate only 0 1 RC out 1 0 PC out 1 1 RC out divided by 2 (GFTEST) CP mode Active Active Active Active High High High High imp. imp. imp. imp.
MCCS (Modulation Compensation Current (Internal Connection) E5 E4 E3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Settings) MCCS 60% 70% 80% 90% 100% 110% 120% 130%
DEMOD DAC Voltage Settings (DEMODDAC)
Demod DAC Voltage (Internal Connection) E10 E9 E8 E7 E6 fIFcenter % 0 0 0 0 0 -6.0 0 0 0 0 1 ... 0 0 0 1 0 ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 6.0
16 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
3-Wire Bus Protocol Timing Diagram
DATA CLOCK ENABLE TPER TL TS TC TH TT
16525
TEC
Figure 4.
Description Clock period Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols
Symbol TPER TS TH TC TL TEC TT
Min. Value 125 60 60 125 200 0 250
Unit ns ns ns ns ns ns ns
Absolute Maximum Ratings
All voltages are referred to GND Parameter Supply voltage regulator Pin 10 Supply voltage Pins 7, 12, 14, 33 and 42 Logic input voltage Pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 Junction temperature Storage temperature Symbol VS_REG VS VIN Tjmax Tstg Min. 3.2 3.0 - 0.3 Max. 4.7 4.7 VS 150 150 Unit V V V _C _C
-40
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value t.b.d. Unit K/W
Operating Range
Parameter Supply voltage regulator Pins 10 Supply voltage Pins 7, 12, 14, 33 and 42 Ambient temperature Symbol VS VS Tamb Min. 3.2 3.0 -25 Typ. 3.6 3.0 Max. 4.6 4.6 +85 Unit V V _C
Rev. A1, 04-Jul-00
17 (24)
Preliminary Information
T2801
Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Receiver IR mixer Pins 29, 30, 40 and 41 Input impedance Pins 29 and 30 Zin 50 Input matching Pins 29 and 30 VSWRin <2:1 Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Pins 40 and 41 NFDSB= 10 dB NFSSB Conversion gain Rload = 200 Gconv 12 dB Output interception point Pins 40 and 41 OIP3 10 dBm IF amplifier Pins 26, 27, 34 and 35 Input impedance Pins 34 and 35 Zin 200 400 Lower cut-off frequency fl3dB 90 MHz Upper cut-off frequency fu3dB 130 MHz Power gain Gp 85 dB Bandwidth of external tank cirPins 26 and 27 BW3dB 10 MHz cuit Noise figure NF 9 dB RSSI Pins 25, 34 and 35 RSSI sensitivity at IF_IN1, IF_IN2 Pmin 20 dBV Pins 34 and 35 RSSI compression at IF_IN1, IF_IN2 Pmax 100 dBV Pins 34 and 35 RSSI dynamic range DR 80 dB RSSI resolution Slope of the RSSI has to be Acc 2 dB steady RSSI rise time Pin = 30 to 100 dBV, Pin 25 tr 1 s RSSI fall time Pin = 100 to 30 dBV, Pin 25 tf 1 s Quiescent output current @ Pin < 20 dBV at IF_IN1, Iout 30 A IF_IN2 Pin 25 Maximum output current @ Pin = 100 dBV at IF_IN1, Iout 150 A IF_IN2 Pin 25 FM demodulator, BB-Filter Pins 19, 20, 23 and 24 Co-channel rejection ratio @ Pin = -75 dBm at CCRR 10 dB IR-mixer input Sensitivity Quality factor of external S 0.5 V/MHz tank circuit approx. 20, fres = FIF/2, Pin 24 Amplitude of recovered signal Nominal deviation of signal A 288 mVss 288 kHz, Pin 24 Corner frequency Pin 23: C = 68 pF fc 680 kHz Output voltage DC range Pin 24 FMoutDC 1 Vs-1 V Output impedance Pin 21 Zout 1.5 k AM rejection ratio Pin 21 AMRR t.b.d. dB DAC for FM demodulator (internally connected) (5-bit programming see bus protocol E5 to E10) DAC range TDAC 6 %
18 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol Min. Typ. Max. Transmitter/ PLL VCO Frequency range fvco 1750 2000 Tuning gain Pin 17 Gtune 40 Frequency control Pin 17 Vtune 0.4 2.8 voltage range DAC for VCO pretune (internally connected) (3-bit bus programming se bus protocol D3 to D5) DAC tuning range fvco,DAC 5 PLL Pin 4 Scaling factor prescaler SPSC 32 / 33 Scaling factor main SMC 32 / 33 / 34 / 35 counter Scaling factor swallow SSC 0 31 counter External reference input AC coupled sinewave fREF_CLK 13.824 frequency Pin 4 27.648 External reference input AC coupled sinewave voltage Pin 4 Scaling factor reference counter Charge pump (active when RX, TX) Pin 13 Output current VI_CP_SW = `0', VCP = VVS_CP / 2 Current scaling factor ICP = CPCS * ICP_TYP (see bus protocol D0 ... D2) Leakage current Gaussian transmit filter (Gaussian shape BT = 0.5) Tx data filter clock 12 taps in filter Frequency deviation Polarity (see bus protocol D13) Frequency deviation GFFM = GFFM_TYP * scaling GFCS (see bus protocol D6 ... D8) Modulation compensation circuit Oversampling Digital sum variation Current scaling factor (see bus protocol E3 ... E5) VREF_CLK SRC 50 3/4/6/8 250 Unit
MHz MHz/V V
%
MHz MHz mVRMS
ICP_1 CPCS 60
1 130 100 13.824 288 60 130
mA %
IL fTXFCLK GFFM_TYP GFCS
pA MHz kHz %
OVS DSV MCCS
6 60 85 130 %
Rev. A1, 04-Jul-00
19 (24)
Preliminary Information
T2801
Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol VCO switch and TX driver Pin 32 Power gain @ Pin = -40 dBm Gp Output impedance Pin 32 Zout Maximum output power Pin 32 Pmax Gain compression @ TX_RF_OUT, Pin 32 P1dB Output interception point Pin 32 OIP3 Ramp generator Pins 36 and 37 Minimum output voltage According to RAMP_SET Vmin input Maximum output voltage According to RAMP_SET Vmax input Rise time Cramp = 270 pF at Pin 37 tr Fall time Cramp = 270 pF at Pin 37 tf Lock detect and test mode output Pin 5 Lock detect output, locked = `1' LD test mode output unlocked = `0' test modes (see bus protocol E0 ... E2) Leakage current VOH = 4.6 V IL Saturation voltage IOL = 0.5 mA VSL Auxiliary regulator Pins 8, 9 and 10 Output voltage VSREG = 3 V Pin 8 VREG Supply voltage rejection VPin10 = VDC + 0.1 Vpp SVR fPin10 = 0.1 to 10 kHz CPin8 = 100 nF VCO regulator Pins 14, 15 and 12 Output voltage VSVCO = 3 V Pin 15 VREG_VCO 3-wire bus Clock fClock Min. Typ. 30 100 3 1 10 0.2 1.95 5 5 Max. Unit dB dBm dBm dBm V V s s
5 0.4 2.9 3.0 tbd 3.1
A V V dB
2.6
2.7 1.152
2.8 6.912
V MHz
20 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol Min. Typ. Logic input levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, DATA_HOLD) Pins 1, 2, 3, 38, 39, 44, 47 and 48 High input level = `1' ViH 1.5 Low input level = `0' ViL High input current = `1' IiH -5 Low input current = `0' IiL -5 Standby control Pins 6, 45 and 46 Power up PU_REG = `1` Pin 6 VPU_REG PU_RX/TX = `1` Pin 45 VPU_RX/TX 2.0 PU_PLL = `1` Pin 46 VPU_PLL High input level Standby PU_REG = `0` Pin 6 VPU_REG,OFF PU_RX/TX = `0` Pin 45 VPU_RX/TX,OFF Pin 46 VPU_PLL,OFF PU_PLL = `0` Low input level Power up PU_REG = `1` VPU = 3 V Pin 6 IPU_REG 20 30 VPU = 5.5 V Pin 45 IPU_RX/TX 60 80 PU_RX/TX = `1` PU_PLL = `1` High input current Standby PU_xxxx = `0' Low input current Settling time VS = 0 active operation Settling time standby active operation Settling time active operation standby Power supply Total supply current VPU = 3 V VPU = 5.5 V VPU = 0 V VPU = 0.5 V Pin 46 IPU_PLL 100 200 125 300 Max. Unit
0.5 5 5
V V A A
V
0.7
V
40 100 150 400 0.1 1
A A A A A A s s s
Pin 6, Pins 45, 46
IPU,OFF
Switched from VS = 0 to VS = 3V Switched from PU = `0' to PU = `1'
tsoa
< 10
tssa
< 10
Standby current, mode 1 mode 2 Supply current CP
Switched from tsas PU = `1' to standby Pins 7, 10, 12, 14, 33 and 42 RX IS RSSI only IS TX IS TX (MCC, GF active) IS PU_RX/TX = GND IS PU = GND, IS DATA_HOLD = VS VVS_CP = 3 V, PLL in ICP lock condition Pin 13
<2
85 82 54 58 1 50 1
10 100
mA mA mA mA A A A
Rev. A1, 04-Jul-00
21 (24)
Preliminary Information
T2801
Typical Application Circuit
100nH 18pF
68pF REG_DEC DAC_DEC 100n 100p
T2801
Figure 5. Typical application circuit
22 (24)
Rev. A1, 04-Jul-00
Preliminary Information
T2801
Package Information
Rev. A1, 04-Jul-00
23 (24)
Preliminary Information
T2801
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
1.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
24 (24)
Rev. A1, 04-Jul-00
Preliminary Information

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